In many integrated circuit packages, it is desirable to provide a system, or reference clock signal. The reference clock signal is used by many devices to derive their respective timing. For example, a reference clock signal may be provided to memory devices, processors, or other circuitry located on a chip. Oftentimes it is desirable to delay the reference clock signal in a manner that creates multiple iterations of the clock signal. These multiple iterations of the reference clock are separated by a known period of time, or phase. For example, a known way of creating multiple iterations of a reference clock is to supply the reference clock to a delay locked loop (DLL). A DLL, as known in the art, is a device that takes the reference clock signal and passes the signal through one or multiple delay lines connected in series. With multiple delay lines connected in series, each delay line supplies a subsequent delay line, such that multiple iterations of the reference clock signal appear at different times. Each of these different times represents a boundary between two consecutive phases. One possible DLL configuration will take a reference clock signal input and create a quadrature output in which there are four iterations of the reference clock signal each iteration being separated by 90 degrees.
A problem, however, with DLL's is that any error in any signal, be it either the reference clock signal or any of the output signals, present will manifest in one, or more, of the output signals, resulting in, for the case of the above described quadrature output signals, one or more phases being shortened or lengthened by an amount equal to the error introduced.
Therefore, it would be desirable to minimize the error present in the DLL output.